1. Field of the Invention
This invention relates to a method of manufacturing semiconductor devices such as single crystal or polycrystalline silicon substrates having trenches and multi-layer leads thereon, and more particularly to a method 0f rounding the angular corner portions of trenches or the step portions of leads during etching.
2. Description of the Prior Art In recent years, semiconductor devices such as MOS dynamic random access memories (DRAM) have progressed in miniaturization and higher integration of elements in accordance with a scaling rule of reduction. The miniaturization of a MOS capacitor, which is one of the essential elements of a DRAM, has also progressed significantly. Here, it is assumed that the thickness and area of the gate oxide film of a MOS capacitor are t.sub.ox and S, respectively, and the scaling factor is .alpha.. The thickness and area of the gate oxide film after reduction will be t.sub.ox /.alpha. and S/.alpha..sup.2, respectively. The capacitance of the MOS capacitor can be expressed by C=.epsilon.S/t.sub.ox, where .epsilon. represents a dielectric constant. Thus, the capacitance C' after the reduction will be C'=C/.alpha.. When the capacitance of MOS capacitor reduces to 1/.alpha., data stored in the MOS DRAM are subjected to errors caused by undesirable penetrating rays, such as alpha rays. Moreover, when the capacitance of a MOS capacitor decreases, the ratio of this capacitance to the stray capacitance that inherently exists between the bit lines and the substrate becomes small. This reduces the accuracy in sensing data, and causes erroneous operations of the MOS DRAM. Therefore, the area of the gate oxide film, which is the area of the MOS capacitor, is generally not reduced to S/.alpha..sup.2 However, from generation to generation, the further reduction of elements has been continuously required. Thus, it is increasingly difficult to obtain highly reliable semiconductor devices, such as DRAMs.
To increase the capacitance of the MOS capacitor, the use of an insulating film having a large dielectric constant (such as Ta.sub.2 O.sub.5, for example) has been considered. However, more time is necessary until this film can be put into practical use. Meanwhile, the use of an extremely thin silicon oxide film of 10 nm or less having high reliability has also been considered. However, such a film requires pure water of high purity or chemicals, and also requires a clean room of very high cleanliness. Thus, this film is also very far from the stage of practical application.
Therefore, a so-called trench capacitor technique has been considered to increase the capacitance of the MOS capacitor. In this technique, a trench is formed on the surface of the semiconductor substrate so as to practically increase the area of the capacitor without an increase in the whole size of elements. However, when a trench having sidewalls perpendicular to the substrate is formed by anisotropic etching, such as reactive ion etching (RIE), the following problem arises. Specifically, the corners of upper and bottom portions of the trench have an extremely small radius of curvature. Thus, when the gate film is formed by thermal oxidation, the oxide films formed on the corners become thinner than the flat portion. This phenomenon can be explained as follows. In general, when silicon is oxidized to form an oxide film, the volume of the film to be formed is about 2.3 times that of the original silicon. Thus, when the oxidation progresses, compression stresses are applied on the oxide film side of the interface between the silicon and silicon oxide film, and stress concentrations occur therein. Consequently, the oxidation thereof is suppressed.
As described above, the oxide films at the corners of the bottom and upper portions of the trench become thinner than the flat portions. Thus, the dielectric breakdown voltage of these corner portions decreases. The thinned film also causes a large leakage current to flow even in a weak electric field. If the gate oxide film is made thicker, the leakage current in the operating voltage can be suppressed to a sufficiently small level. However, this causes the film of the flat portions in the trench to be excessively thicker. This thickness cancels the effect of the increase in the capacitance of MOS capacitor, which is obtained by trenching so as to increase the surface area of the substrate.
On the other hand, a so-called stacked capacitor technique has been considered. In this technique, the capacitance of the MOS capacitor can be increased within a limited space. Specifically, one electrode of polycrystalline silicon is stacked on the element or element isolation region, and the surface thereof is oxidized. Thereafter, another electrode is similarly formed on the stacked element, so as to constitute a MOS capacitor. However, also in the case of polycrystalline silicon electrodes, the treatment of RIE inevitably produces angular corners on such electrodes. If the polycrystalline silicon surface is oxidized leaving the angular corners as they are, the oxide films of corners inevitably become thinner. This is a phenomenon similar to the case of the single crystal silicon. As a result, the insulating effect of the corners also deteriorates.
As described above, when a trench or a step portion is formed on the semiconductor substrate, the radius of curvature Of the corners at the bottom or upper portions of the trench or step portions becomes significantly reduced. These angular corners have caused problems in manufacturing elements of MOS DRAMs or the like.